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| MC74HC595A 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High-Performance Silicon-Gate CMOS The MC74HC595A consists of an 8-bit shift register and an 8-bit D-type latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs. http://onsemi.com MARKING DIAGRAMS 16 16 1 PDIP-16 N SUFFIX CASE 648 MC74HC595AN AWLYYWW 1 16 * * * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 328 FETs or 82 Equivalent Gates Improvements over HC595 -- Improved Propagation Delays -- 50% Lower Quiescent Power -- Improved Input Noise and Latchup Immunity LOGIC DIAGRAM SERIAL DATA INPUT A 14 15 1 2 3 SHIFT REGISTER 4 LATCH QA QB QC QD PARALLEL DATA OUTPUTS 16 1 SO-16 D SUFFIX CASE 751B 1 HC595A AWLYWW 16 TSSOP-16 DT SUFFIX CASE 948F 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week HC 595A ALYW 16 1 PIN ASSIGNMENT QB QC QD QE QF QG QH GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QA A OUTPUT ENABLE LATCH CLOCK SHIFT CLOCK RESET SQH QE 5 QF 6 QG 7 QH SHIFT 11 CLOCK 10 RESET LATCH 12 CLOCK OUTPUT 13 ENABLE 9 SQH SERIAL DATA OUTPUT ORDERING INFORMATION Device MC74HC595AN MC74HC595AD MC74HC595ADR2 MC74HC595ADT MC74HC595ADTR2 Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel VCC = PIN 16 GND = PIN 8 (c) Semiconductor Components Industries, LLC, 2000 1 March, 2000 - Rev. 8 Publication Order Number: MC74HC595A/D MC74HC595A II II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II I I I I I IIII II I IIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIII III I II I II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII II I IIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIII II I IIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout TA VCC Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) - 55 0 0 0 + 125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VIH Parameter Test Conditions VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 - 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 v 85_C v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 Unit V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A V VOH Minimum High-Level Output Voltage, QA - QH Vin = VIH or VIL |Iout| 20 A v V Vin = VIH or VIL |Iout| |Iout| |Iout| v 2.4 mA v 6.0 mA v 7.8 mA v 2.4 mA v 6.0 mA v 7.8 mA 2.48 3.98 5.48 0.1 0.1 0.1 2.34 3.84 5.34 0.1 0.1 0.1 VOL Maximum Low-Level Output Voltage, QA - QH Vin = VIH or VIL |Iout| 20 A v V Vin = VIH or VIL |Iout| |Iout| |Iout| 0.26 0.26 0.26 0.33 0.33 0.33 http://onsemi.com 2 II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II II II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II II II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I II I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII II II I I I I III I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Symbol VOH tPLH, tPHL tPLH, tPHL tTLH, tTHL tPZL, tPZH tPLZ, tPHZ VOL tPHL fmax ICC IOZ Iin Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current, QA - QH Maximum Input Leakage Current Maximum Low-Level Output Voltage, SQH Minimum High-Level Output Voltage, SQH Maximum Output Transition Time, QA - QH (Figures 3 and 7) Maximum Propagation Delay, Output Enable to QA - QH (Figures 4 and 8) Maximum Propagation Delay, Output Enable to QA - QH (Figures 4 and 8) Maximum Propagation Delay, Latch Clock to QA - QH (Figures 3 and 7) Maximum Propagation Delay, Reset to SQH (Figures 2 and 7) Maximum Propagation Delay, Shift Clock to SQH (Figures 1 and 7) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 7) Parameter Parameter Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VIH or VIL IIoutI 20 A Vin = VIH or VIL IIoutI 20 A Vin = VCC or GND lout = 0 A Vin = VCC or GND Vin = VIH or VIL |Iout| 2.4 mA IIoutI 4.0 mA IIoutIv 5.2 mA Vin = VIH or VIL |Iout| 2.4 mA IIoutI 4.0 mA IIoutIv 5.2 mA v v Test Conditions http://onsemi.com MC74HC595A 3 v v v v VCC V VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 6.0 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C - 55 to 25_C 0.5 0.1 0.26 0.26 0.26 2.98 3.98 5.48 135 90 27 23 150 100 30 26 140 100 28 24 145 100 29 25 140 100 28 24 6.0 15 30 35 4.0 0.1 0.1 0.1 1.9 4.4 5.9 60 23 12 10 Guaranteed Limit Guaranteed Limit v 85_C v 125_C v 85_C v 125_C 5.0 1.0 0.33 0.33 0.33 2.34 3.84 5.34 170 110 34 29 190 125 38 33 175 125 35 30 180 125 36 31 175 125 35 30 4.8 10 24 28 0.1 0.1 0.1 1.9 4.4 5.9 40 75 27 15 13 1.0 10 205 130 41 35 225 150 45 38 210 150 42 36 220 150 44 38 210 150 42 36 160 4.0 8.0 20 24 0.4 0.4 0.4 0.1 0.1 0.1 2.2 3.7 5.2 1.9 4.4 5.9 90 31 18 15 MHz Unit Unit A A A ns ns ns ns ns ns V V III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II II II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I 300 pF 2 f + I CC V CC . For load considerations, see Chapter 2 of the * Used to determine the no-load dynamic power consumption: P D = C PD V CC ON Semiconductor High-Speed CMOS Data Book (DL129/D). II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6.0 ns) AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol Symbol tTLH, tTHL CPD Cout trec tr, tf Cin tsu tsu tw tw tw th Power Dissipation Capacitance (Per Package)* Maximum Input Rise and Fall Times (Figure 1) Minimum Pulse Width, Latch Clock (Figure 6) Minimum Pulse Width, Shift Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2) Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5) Minimum Setup Time, Shift Clock to Latch Clock (Figure 6) Minimum Setup Time, Serial Data Input A to Shift Clock (Figure 5) Maximum Three-State Output Capacitance (Output in High-Impedance State), QA - QH Maximum Input Capacitance Maximum Output Transition Time, SQH (Figures 1 and 7) Parameter Parameter http://onsemi.com MC74HC595A 4 VCC V VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- -- 25_C to - 55_C - 55 to 25_C Typical @ 25C, VCC = 5.0 V 1000 800 500 400 5.0 5.0 5.0 5.0 50 40 10 9.0 50 40 10 9.0 50 40 10 9.0 50 40 10 9.0 60 45 12 10 75 60 15 13 15 10 75 27 15 13 Guaranteed Limit Guaranteed Limit v 85_C v 125_C v 85_C v 125_C 1000 800 500 400 5.0 5.0 5.0 5.0 65 50 13 11 65 50 13 11 75 60 15 13 65 50 13 11 95 70 19 16 65 50 13 11 15 10 95 32 19 16 1000 800 500 400 110 80 22 19 110 36 22 19 5.0 5.0 5.0 5.0 75 60 15 13 75 60 15 13 90 70 18 15 75 60 15 13 75 60 15 13 15 10 Unit Unit pF pF ns ns ns ns ns ns ns ns ns MC74HC595A FUNCTION TABLE Inputs Serial Input A X D X X Shift Clock X L, H, L, H, Latch Clock L, H, L, H, L, H, Output Enable L L L L D SRN Shift Register Contents L SRA; SRN+1 U U SRN Resulting Function Latch Register Contents U U U LRN Serial Output SQH L SRG U U SRH Parallel Outputs QA - QH U U U SRN Operation Reset shift register Shift data into shift register Shift register remains unchanged Transfer shift register contents to latch register Latch register remains unchanged Enable parallel outputs Force outputs into high impedance state Reset L H H H X X X X X X X X X L, H, X X L L H = Low-to-High = High-to-Low * * * U ** ** * * * U Enabled Z SR = shift register contents LR = latch register contents D = data (L, H) logic level U = remains unchanged * = depends on Reset and Shift Clock inputs ** = depends on Latch Clock input PIN DESCRIPTIONS INPUTS A (Pin 14) Output Enable (Pin 13) Serial Data Input. The data on this pin is shifted into the 8-bit serial shift register. CONTROL INPUTS Shift Clock (Pin 11) Active-low Output Enable. A low on this input allows the data from the latches to be presented at the outputs. A high on this input forces the outputs (QA-QH) into the high-impedance state. The serial output is not affected by this control unit. OUTPUTS QA - QH (Pins 15, 1, 2, 3, 4, 5, 6, 7) Shift Register Clock Input. A low- to-high transition on this input causes the data at the Serial Input pin to be shifted into the 8-bit shift register. Reset (Pin 10) Noninverted, 3-state, latch outputs. SQH (Pin 9) Active-low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only. The 8-bit latch is not affected. Latch Clock (Pin 12) Noninverted, Serial Data Output. This is the output of the eighth stage of the 8-bit shift register. This output does not have three-state capability. Storage Latch Clock Input. A low-to-high transition on this input latches the shift register data. http://onsemi.com 5 MC74HC595A SWITCHING WAVEFORMS tr SHIFT CLOCK 90% 50% 10% tw 1/fmax tPLH OUTPUT SQH 90% 50% 10% tTLH tTHL tPHL tf VCC GND RESET tPHL OUTPUT SQH SHIFT CLOCK 50% trec VCC 50% GND 50% GND tw VCC Figure 1. VCC GND tPLH 90% QA-QH 50% OUTPUTS 10% tTLH tTHL tPHL OUTPUT ENABLE Figure 2. VCC 50% GND tPZL OUTPUT Q 50% tPZH OUTPUT Q 50% tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE LATCH CLOCK 50% Figure 3. SHIFT CLOCK Figure 4. VCC 50% GND tsu LATCH CLOCK 50% GND tw VCC VALID SERIAL INPUT A VCC 50% GND tsu SWITCH CLOCK th 50% VCC GND Figure 5. Figure 6. TEST CIRCUITS TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL* CL* *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 7. Figure 8. http://onsemi.com 6 MC74HC595A EXPANDED LOGIC DIAGRAM OUTPUT ENABLE LATCH CLOCK SERIAL DATA INPUT A 13 12 14 D SRA R D SRB R D SRC R D SRD R D SRE R D SRF R D SRG R D Q D LRA Q 15 QA Q D LRB Q 1 QB Q D LRC Q 2 QC Q D LRD Q 3 QD PARALLEL DATA OUTPUTS Q D LRE Q 4 QE Q D LRF Q 5 QF Q D LRG Q 6 QG SHIFT CLOCK Q SRH D LRH Q 7 QH 11 R 10 RESET 9 SERIAL DATA OUTPUT SQH http://onsemi.com 7 MC74HC595A TIMING DIAGRAM SHIFT CLOCK SERIAL DATA INPUT A RESET LATCH CLOCK OUTPUT ENABLE QA QB QC QD QE QF QG QH SERIAL DATA OUTPUT SQH NOTE: implies that the output is in a high-impedance state. http://onsemi.com 8 MC74HC595A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 10 0 10 0 0.020 0.040 1.01 0.51 B 1 8 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 -B - 1 8 P 8 PL 0.25 (0.010) M B M G F K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S http://onsemi.com 9 MC74HC595A PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.25 (0.010) 0.15 (0.006) T U S A -V- N F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E http://onsemi.com 10 EEE CCC EEE CCC M -W- DIM A B C D F G H J J1 K K1 L M MC74HC595A Notes http://onsemi.com 11 MC74HC595A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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